Floppy disks encoded in modified FM (MFM) are in widespread use with personal computers (PC's). It is necessary to synchronize the transfer of information from the disk in the disk drive of the computer with the internal clock of the computer. To accomplish this, a voltage controlled oscillator within the computer, which is used to provide the clock signals, is synchronized in frequency with the frequency of data encoded on the disk. It is possible for variations of as much as plus and minus ten percent to occur between the internal clock frequency of the computer and the synchronization field frequency read from the disk. This may be caused by differences between the speed of operation of the disk drive motor in the computer, where the information originally was stored, and the motor in the drive of the computer with which the disk is to be used.
In the past, synchronization typically has been handled by voltage controlled oscillators in an analog phase-locked loop (PLL). The data from the disk, which is used to synchronize the operation of the voltage controlled oscillator of the computer, frequently has pulses missing in adjacent cycles or comparison windows. To avoid erroneous operation of the PLL phase detector in such a situation, a typical solution has been to use a one-quarter cycle delay line to delay the data; so that a data pulse is known to be present in a given comparison window before the phase detector receives it as input. With this information, the phase detector may be disabled when no data pulse is present in a given comparison window. An alternative is that pulses can be inserted from the reference source to be substituted for the missing data pulses. The delay line, however, is an analog delay line, and whether this delay line is used in conjunction with a pulse inserter or a disabling circuit, additional circuit components are necessary to effect the proper operation of the phase detector.
The use of analog components, however, does have some disadvantages. One of these is that analog circuits are difficult to fabricate with precision and predictability in an integrated circuit. A second disadvantage is that analog components are subject to significant drift with temperature. Consequently, any analog design must allow sufficient margin for such temperature-caused drift.
Digital phase detectors for PLL operation have been developed. Three types of digital phase detector circuits generally are used. The first of these (called Type 2) is an EXCLUSIVE OR gate type of circuit. The second (Type 3) is an edge-triggered JK flip-flop. The third (known as Type 4) is a phase/frequency detector. Type 4 phase discriminators are generally considered superior to both Type 2 and Type 3 phase detectors. Type 4 phase detectors are independent of the duty cycle ratio of the waveforms applied to the inputs, and, additionally, exhibit marked sensitivity to frequency for even the smallest offset of the frequencies between the two inputs. Consequently, Type 4 phase detector circuits are frequently referred to as phase/frequency detectors.
A conventional Type 4 phase detector, however, will fail on any given window or comparison interval when no data pulse appears. When this situation occurs, the charge pump (in an analog PLL) is caused to pump up (or down) erroneously. In a digital PLL, the phase error calculated is incorrect in such a window, and causes the oscillator frequency to be changed incorrectly.
Consequently, there are disadvantages to both analog and digital phase detectors when these detectors are used with a system for synchronization with the data encoded on a floppy disk, since that data, as mentioned above, frequently includes comparison windows where data pulses are missing.
It is desirable to provide a digital phase detection circuit, which overcomes the disadvantages of the prior art mentioned above, and which is simple to implement and operate.